It calculates one or more carries before the sum, which reduces the wait time/Ripple delay to calculate the result of the larger value bits of the adder.- Google Patents US5018093A - High performance self-checking adder having small circuit areaA ripple carry adder is a digital circuit that produces the arithmetic sum of two binary numbers. A carry-look ahead adder improves speed by reducing the amount of time required to determine to carry bits. Why there is always a scope to tradeoff between the speed 8.A carry-look ahead adder (CLA) or fast adder is a type of adder used in digital logic.

Reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION, A CORP. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by International Business Machines Corp filed Critical International Business Machines Corp Priority to US07/459,872 priority Critical patent/US5018093A/en Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, A CORP. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)Original Assignee International Business Machines Corp Priority date (The priority date is an assumption and is not a legal conclusion. Shih Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Expired - Fee Related Application number US07/459,872 Inventor Feng-Hsien W.

238000010586 diagram Methods 0.000 description 4 241001442055 Vipera berus Species 0.000 title claims abstract description 135 Application granted granted Critical Publication of US5018093A publication Critical patent/US5018093A/en Anticipated expiration legal-status Critical Status Expired - Fee Related legal-status Critical Current Links Assignors: SHIH, FENG-HSIEN W.

238000006011 modification reaction Methods 0.000 description 1 230000004048 modification Effects 0.000 description 1 238000001514 detection method Methods 0.000 description 1 230000001419 dependent Effects 0.000 description 1

G06F11/07— Responding to the occurrence of a fault, e.g. G06F11/00— Error detection Error correction Monitoring 230000003068 static Effects 0.000 description 1

Having a different digit-handling circuit for each denominationFIG. G06F7/505— Adding Subtracting in bit-parallel fashion, i.e. Tube, solid state device using unspecified devices Using binary, ternary, decimal representation using non-contact-making devices, e.g.

After the appropriate sum has been provided to latch A01, the CARRY signal is toggled to '0' and adders 31 and 32 perform a second addition operation with carry-ins equal to 0 and 1, respectively. When CARRY=1 and Cin=0, however, the sum 32c output from adder 32 is provided to latch A01 on line 33A. Therefore when CARRY=1, and Cin=1, the sum 31c output from adder 31 is provided to latch A01 on line 33A. The output STMUX 33 provides the correct sum to latch A01 when CARRY=1. These adders first perform the addition while the CARRY signal is equal to 1. In each stage, each of the ripple adders 31 and 32 adds Ai-Aj to Bi-Bj.

For example if Cin=1, the sum latched in latch A01 is the sum produced by adder 31 and the sum latched in latch A02 is the sum produced by adder 32. Thus, the sum latched in latch A01 is always a sum produced from a different adder than the sum latched in latch A02. When CARRY=0 and Cin=0, STMUX 33 provides the sum 31c from adder 31 to latch A02. When CARRY=0, and Cin=1, STMUX 33 provides the sum 32 c from adder 32 to latch A02 via line 33B.

The method claimed in claim 15, further comprising the step of providing one of said selected outputs as sum output bits output by said stage being checked for faults.

Binary Ripple Carry Adder